Paragon ATM OC12 tests

Sandia has procured four ATM OC12 interface boards (ATM OC-12c Protocol Engines from GigaNet, Inc.) for Intel Paragons. This page describes early testing of these interfaces with GigaNet, Intel, Sandia, and ORNL's Center for Computational Science. One objective is to interconnect multiple Paragons over ATM at OC12 speeds to concurrently work on a single application using PVM. Long term goals include cross-country Paragon ATM interconnects. Candidate applications include PCTH, global climate modeling ( CHAMMP ), and materials science.

The GigaNet ATM OC-12c Protocol Engine is an MP3 I/O node (2 slots) that is attached to the Paragon mesh. The GigaNet interface board supports all appropriate full duplex STS-12c/OC-12c CCITT physical layer requirements. The hardware interface has receive and transmit buffers, SAR logic, TCP/IP acceleration logic, and logic for direct access to the Paragon mesh. For further details on the GigaNet interface see "A High Performance ATM Protocol Engine for the Intel Paragon" (ISUG, Jun '95).

The GigaNet ATM API provides a low level, but high performance applications interface to the ATM/AAL5 layer. (Click here for 160K postscript API manual.) ATM/AAL5 is a connection-oriented best effort packet transfer service. Packets can be up to 65,536 bytes in length. The programmer is responsible for providing a queue of receive buffers, for polling to see if data is available, and for managing time-outs and re-transmissions. No operating system services are used by the API, in particular, the ATM message passing (like NX) is not part of the UNIX I/O paradigm. The API presently supports only 255 circuits per ATM interface, though a Paragon may have more than one GigaNet ATM interface. GigaNet is developing an IP over ATM service based on RFC1577 .
Here is the latest (7/16/96) document describing TCP/IP over the GigaNet ATM.

Participants

Principal Investiagtor Tom Pratt, Sandia, tjpratt@sandia.gov
Principal Investiagtor Steve Gossage, Sandia, sagossa@sandia.gov
Buddy Bland, ORNL, aib@ornl.gov, systems and logistics
Tom Dunigan, ORNL, thd@ornl.gov, benchmarking
David Fair, Intel, fair@ssd.intel.com, Intel SSD rep.
Dave Follett, Giganet, dfollett@world.std.com, hardware
Maria Gutierrez, Giganet, mgutier@world.std.com, hardware
Alden Jackson, Sandia/CA, awjacks@ca.sandia.gov, ATM
Lawrence MacIntyre, ORNL, lpz@ornl.gov, ATM
Peter Molnar, Intel at ORNL, molnarp@ccs.ornl.gov, systems
Phil Papadopoulos, ORNL, phil@msr.csm.ornl.gov, PVM
Rich Prohaska, Giganet, prohaska@world.std.com, software
Tony Ralph, Intel at Sandia, tonyr@cs.sandia.gov, ATM
Allen Robinson, Sandia, acrobin@sandia.gov, applications
Tim Sheehan, ORNL, t6i@ornl.gov, applications

If you wish to send email to all participants try xcparagon@cs.sandia.gov

Schedule

Test summaries

Here are August, 1997 VCI info and Chuck Fisher's circuit maps for ORNL and Sandia. Here are 11/16/95 ATM/PVC switch configurations and the current configurations of the two Paragons.
Last Modified by dunigan thd@ornl.gov (touches: )
back to Tom Dunigan's page or the ORNL home page